Ritwik Raj Location
- San Jose, CA, US
Ritwik Raj Work
- 2021 -now Design Verification Engineer @
- 2019 -2021 Sr. ASIC Engineer @
- 2016 -2019 ASIC Engineer 2 @
- 2015 -2015 Intern @
Ritwik Raj Education
- North Carolina State University
Master's of Science (Electrical and Electronics Engineering)
2014-2016 - Nirma University
Bachelor's degree (Electrical and Electronics Engineering)
2009-2013 - Bhartiya Vidya Bhavans
High School
Ritwik Raj Skills
- Universal Verification Methodology (UVM)
- C++
- Python
- Application-Specific Integrated Circuits (ASIC)
- Verilog
- C
- SystemVerilog
- PADS Layout
- PowerPoint
- Field Programmable Gate Arrays Fpga
- RF design
- Analog Circuit Design
- Matlab
- PCB design
- ASIC
- Power Electronics
- Power Management
- Xilinx ISE
- Digital Control
- Microsoft Office
- Programming
- Microsoft Word
- Java
- Microsoft Excel
- Application Specific Integrated Circuits Asic
- Testing
- FPGA
- Pads Logic
- Universal Verification Methodology Uvm
- IC
- Application Specific Integrated Circuits
- Universal Verification Methodology
Ritwik Raj Summary
- Ritwik Raj, based in San Jose, CA, US, is currently a Design Verification Engineer at Meta. Ritwik Raj brings experience from previous roles at Juniper Networks and Finisar Corporation (NASDAQ: FNSR). Ritwik Raj holds a 2014 - 2016 Master's of Science in Electrical and Electronics Engineering @ North Carolina State University. With a robust skill set that includes Universal Verification Methodology (UVM), C++, Python, Application-Specific Integrated Circuits (ASIC), Verilog and more. Ritwik Raj has 3 emails and 1 mobile phone numbers on RocketReach.
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