Rishit Patel Email & Phone Number
Staff CPU Physical Design Engineer @ Qualcomm
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Rishit Patel Location
- Austin, TX, US
Rishit Patel Work
- 2020 -2021 Senior Engineer @
- 2021 -2023 COT IP Physical Design Engineer @
- 2023 -2024 SoC Timing Engineer @
- 2024 -now Staff CPU Physical Design Engineer @
- 2017 -2020 Engineer - CPU Physical Design @
- 2017 -2017 Physical Design Engineer @
- 2016 -2017 Graduate Teaching Assistant @
- 2015 -2016 Graduate Research Assistant @
Rishit Patel Education
- Wright State University
Master’s Degree (Electrical and Electronics Engineering)
2014-2017 - Vishwakarma government engineering college
Bachelor of Engineering (B.E.) (Instrumentation and Control)
Rishit Patel Skills
- Logic Design
- Cadence Virtuoso
- Signal Integrity
- Computer Architecture
- Linux
- Custom Designersynopsys
- Algorithms
- Field Programmable Gate Arrays Fpga
- Verification and Validation V&V
- C
- System on a Chip Soc
- System Verilog
- Physical Verification
- HSPICE
- Perl
- RTL design
- Matlab
- Microprocessors
- ASIC
- Verilog
- TCP/IP
- TCL
- Cadence Encounter
- Ic Compiler
- Application Specific Integrated Circuits Asic
- FPGA
- SoC
- VHDL
- Power Integrity
- C++
- Ise Design Suite
- Vlsi Testing
- Physical Design
- Research
- Static Timing Analysis
- Unix
- Low Power Design
- Design Compiler
- Digital Circuit Design
- Field Programmable Gate Arrays
- Application Specific Integrated Circuits
- System on a Chip
- Verification and Validation
Rishit Patel Summary
- Rishit Patel, based in Austin, TX, US, is currently a Staff CPU Physical Design Engineer at Qualcomm. Rishit Patel brings experience from previous roles at Qualcomm and Ericsson. Rishit Patel holds a 2014 - 2017 Master’s Degree in Electrical and Electronics Engineering @ Wright State University. With a robust skill set that includes Logic Design, Cadence Virtuoso, Signal Integrity, Computer Architecture, Linux and more. Rishit Patel has 3 emails and 1 mobile phone numbers on RocketReach.
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