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Rishit Patel Location
Austin, TX, US
Rishit Patel Work
Senior Engineer @ (November 2020 - December 2021)
COT IP Physical Design Engineer @ (December 2021 - June 2023)
SoC Timing Engineer @ (June 2023 - June 2024)
Staff CPU Physical Design Engineer @ (June 2024 - Present)
Engineer - CPU Physical Design @ (November 2017 - November 2020)
Physical Design Engineer @ (August 2017 - November 2017)
Graduate Teaching Assistant @ (August 2016 - April 2017)
Graduate Research Assistant @ (August 2015 - July 2016)
Rishit Patel Education
Wright State University
Master’s Degree (Electrical and Electronics Engineering)
2014-2017
Vishwakarma government engineering college
Bachelor of Engineering (B.E.) (Instrumentation and Control)
Rishit Patel Skills
Logic Design
Cadence Virtuoso
Signal Integrity
Computer Architecture
Linux
Custom Designersynopsys
Algorithms
Field Programmable Gate Arrays Fpga
Verification and Validation V&V
C
System on a Chip Soc
System Verilog
Physical Verification
HSPICE
Perl
RTL design
Matlab
Microprocessors
ASIC
Verilog
TCP/IP
TCL
Cadence Encounter
Ic Compiler
Application Specific Integrated Circuits Asic
FPGA
SoC
VHDL
Power Integrity
C++
Ise Design Suite
Vlsi Testing
Physical Design
Research
Static Timing Analysis
Unix
Low Power Design
Design Compiler
Digital Circuit Design
Field Programmable Gate Arrays
Application Specific Integrated Circuits
System on a Chip
Verification and Validation
Rishit Patel Summary
Rishit Patel, based in Austin, TX, US, is currently a Staff CPU Physical Design Engineer at Qualcomm. Rishit Patel brings experience from previous roles at Qualcomm and Ericsson. Rishit Patel holds a 2014 - 2017 Master’s Degree in Electrical and Electronics Engineering @ Wright State University. With a robust skill set that includes Logic Design, Cadence Virtuoso, Signal Integrity, Computer Architecture, Linux and more. Rishit Patel has 3 emails and 1 mobile phone numbers on RocketReach.
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