Rishabh Agarwal Email & Phone Number

Rishabh Agarwal Skills

• Pandas (Software)
• NumPy
• Power Analysis
• ASIC
• Physical Design
• SoC
• VLSI
• Integrated Circuit Design
• Cadence Virtuoso
• SoC floorplanning
• DRC
• C++
• TCL
• Perl
• Unix
• Cadence Encounter
• Redhawk
• Microcontrollers
• C
• VHDL
• Verilog
• RTL Design
• SPICE
• EDA
• ModelSim
• CMOS
• Circuit Design
• Physical Verification
• Semiconductors
• LVS
• Cadence
• System on a Chip (SoC)
• Very-Large-Scale Integration (VLSI)
• Layout Versus Schematic (LVS)
• Application-Specific Integrated Circuits (ASIC)
• Shell Scripting
• Synopsys tools
• Integrated Circuits (IC)
• Simulations
• Algorithms
• Static Timing Analysis
• System on a Chip
• Very Large Scale Integration
• Layout Versus Schematic
• Application Specific Integrated Circuits
• Integrated Circuits