Contractor, Design Engineer @ Xilinx (June 2009 - April 2010)
Application Engineer @ Xilinx (April 2006 - June 2009)
Firmware Engineer @ (August 2005 - April 2006)
Intern Application Engineer @ Xilinx (June 2004 - August 2004)
Rish Patel Education
Santa Clara University
MS (Electrical Engineering)
2009-2011
California Polytechnic State University-San Luis Obispo
BS (Computer Engineering)
2001-2006
Rish Patel Skills
10/25G SerDes
ASIC
C
CPLD
Cross-functional Team Leadership
DDR
DDR/Memory & DMA Throughput
Debugging
Driver/FW/SW integration
Dyslexic Thinking
Embedded Systems
Engineering Management
Ethernet
Execution Tooling/Trackers
FPGA
FPGA (Xilinx/Intel)
Firmware
Hardware
Imaging Data Paths
Intel Quartus Prime
Java
Lossless Compression
Microprocessors
ModelSim
PCIe
PCIe Gen4/Gen5
Processors
Program/Roadmap Ownership
Programming
Python
QuestaSim
Risk & EOL Mitigation
SERDES
Simulations
Software Design
Software Development
TCL
Testing
VHDL
Vendor/Supplier Management
Verilog
Xilinx
Xilinx Vivado
Rish Patel Summary
Rish Patel, based in San Jose, CA, US, is currently a Engineering Manager and System Architect — Image Data Acquisition (IDA) at KLA. Rish Patel brings experience from previous roles at KLA and Cisco Systems. Rish Patel holds a 2009 - 2011 MS in Electrical Engineering @ Santa Clara University. With a robust skill set that includes 10/25G SerDes, ASIC, C, CPLD, Cross-functional Team Leadership and more. Rish Patel has 4 emails and 1 mobile phone numbers on RocketReach.
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