Rish Patel Email & Phone Number
Engineering Manager and System Architect — Image Data Acquisition (IDA) @ KLA
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Rish Patel Location
- San Jose, CA, US
Rish Patel Work
- Engineering Manager and System Architect — Image Data Acquisition (IDA) @ (February 2021 - Present)
- Staff FPGA Engineer — Hardware Acceleration and Compression @ (January 2018 - January 2021)
- Lead FPGA Engineer — Image Acquisition and Image Alignment Compute @ (January 2015 - January 2018)
- FPGA Engineer (Loader, Pixel Formatter) @ (January 2012 - January 2015)
- Design Engineer (Co-op) @ (June 2010 - June 2011)
- Contractor, Design Engineer @ (June 2009 - April 2010)
- Application Engineer @ (April 2006 - June 2009)
- Firmware Engineer @ (August 2005 - April 2006)
- Intern Application Engineer @ (June 2004 - August 2004)
Rish Patel Education
- Santa Clara University
MS (Electrical Engineering)
2009-2011 - California Polytechnic State University-San Luis Obispo
BS (Computer Engineering)
2001-2006
Rish Patel Skills
- Software Design
- C
- Debugging
- Microprocessors
- PCIe
- Processors
- ASIC
- Verilog
- Xilinx
- TCL
- Ethernet
- Programming
- Java
- Embedded Systems
- Testing
- SERDES
- FPGA
- VHDL
- ModelSim
- Python
- Firmware
- Simulations
- Software Development
- Hardware
- CPLD
- DDR
Rish Patel Summary
- Rish Patel, based in San Jose, CA, US, is currently a Engineering Manager and System Architect — Image Data Acquisition (IDA) at KLA. Rish Patel brings experience from previous roles at KLA and Cisco Systems. Rish Patel holds a 2009 - 2011 MS in Electrical Engineering @ Santa Clara University. With a robust skill set that includes Software Design, C, Debugging, Microprocessors, PCIe and more. Rish Patel has 4 emails and 1 mobile phone numbers on RocketReach.
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