Rish Patel Email & Phone Number
Engineering Manager and System Architect — Image Data Acquisition (IDA) @ KLA
5 free lookup(s).
Rish Patel Location
- San Jose, CA, US
Rish Patel Work
- 2021 - now Engineering Manager and System Architect — Image Data Acquisition (IDA) @
- 2018 - 2021 Staff FPGA Engineer — Hardware Acceleration and Compression @
- 2015 - 2018 Lead FPGA Engineer — Image Acquisition and Image Alignment Compute @
- 2012 - 2015 FPGA Engineer (Loader, Pixel Formatter) @
- 2010 - 2011 Design Engineer (Co-op) @
- 2009 - 2010 Contractor, Design Engineer @
- 2006 - 2009 Application Engineer @
- 2005 - 2006 Firmware Engineer @
- 2004 - 2004 Intern Application Engineer @
Rish Patel Education
- Santa Clara University
MS (Electrical Engineering)
2009 - 2011 - California Polytechnic State University-San Luis Obispo
BS (Computer Engineering)
2001 - 2006
Rish Patel Skills
- Software Design
- C
- Debugging
- Microprocessors
- PCIe
- Processors
- ASIC
- Verilog
- Xilinx
- TCL
- Ethernet
- Programming
- Java
- Embedded Systems
- Testing
- SERDES
- FPGA
- VHDL
- ModelSim
- Python
- Firmware
- Simulations
- Software Development
- Hardware
- CPLD
- DDR
Rish Patel Summary
- Rish Patel, based in San Jose, CA, US, is currently a Engineering Manager and System Architect — Image Data Acquisition (IDA) at KLA. Rish Patel brings experience from previous roles at KLA and Cisco Systems. Rish Patel holds a 2009 - 2011 MS in Electrical Engineering @ Santa Clara University. With a robust skill set that includes Software Design, C, Debugging, Microprocessors, PCIe and more. Rish Patel has 2 emails and 1 mobile phone numbers on RocketReach.
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