2020 -2022 Executive Principal Engineer, Logic and Verification @
2019 -2020 Sr. Director. Logic Design and Verification @
2012 -2019 Verification Application Engineer @
2011 -2012 Principal Researcher @ Terasquare
2010 -2011 Principal Engineer @ Human Chips
2009 -2010 Senior Staff Engineer @
2005 -2009 Senior Staff Engineer @ Infineon
2000 -2005 Senior Engineer @
1994 -2000 Research Engineer @ Institute for Advanced Engineering
Rim J. Education
Ajou University
Master of Engineering (Electronics)
1992-1994
Ajou University
Bachelor (Engineering)
1988-1992
Rim J. Skills
Timing Closure
Specman
TCL
VHDL
RTL design
Verilog
SoC
Static Timing Analysis
ASIC
ModelSim
VLSI
SystemVerilog
IC
Functional Verification
Hardware Design
Simulation
Csh
NCSim
Semiconductors
RTL coding
Digital Design
ARM
AHB
I2C
NC-Verilog
CMOS
Primetime
Formal Verification
Logic Synthesis
Integrated Circuit Design
Development
Applications
Nc Verilog
Research
Verification
Rim J. Summary
Rim J., based in South Korea, is currently a Chief Technology Officer at 주식회사 메타앙코르(MetaEncore Co., Ltd). Rim J. brings experience from previous roles at Veri-fun, SEMIFIVE, SemiFive and Synopsys Inc. Rim J. holds a 1992 - 1994 Master of Engineering in Electronics @ Ajou University. With a robust skill set that includes Timing Closure, Specman, TCL, VHDL, RTL design and more. Rim J. has 1 emails and 1 mobile phone numbers on RocketReach.
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