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Rim J. Location
South Korea
Rim J. Work
Chief Technology Officer @ (July 2024 - Present)
Design Verification Engineer @ Veri-fun (August 2022 - June 2024)
Executive Principal Engineer, Logic and Verification @ (October 2020 - August 2022)
Sr. Director. Logic Design and Verification @ (November 2019 - August 2020)
Verification Application Engineer @ (October 2012 - October 2019)
Principal Researcher @ Terasquare (October 2011 - September 2012)
Principal Engineer @ Human Chips (June 2010 - September 2011)
Senior Staff Engineer @ (November 2009 - June 2010)
Senior Staff Engineer @ Infineon (November 2005 - November 2009)
Senior Engineer @ (March 2000 - October 2005)
Research Engineer @ Institute for Advanced Engineering (February 1994 - February 2000)
Rim J. Education
Ajou University
Master of Engineering (Electronics)
1992-1994
Ajou University
Bachelor (Engineering)
1988-1992
Rim J. Skills
Timing Closure
Specman
TCL
VHDL
RTL design
Verilog
SoC
Static Timing Analysis
ASIC
ModelSim
VLSI
SystemVerilog
IC
Functional Verification
Hardware Design
Simulation
Csh
NCSim
Semiconductors
RTL coding
Digital Design
ARM
AHB
I2C
NC-Verilog
CMOS
Primetime
Formal Verification
Logic Synthesis
Integrated Circuit Design
Development
Applications
Nc Verilog
Research
Verification
Rim J. Summary
Rim J., based in South Korea, is currently a Chief Technology Officer at 주식회사 메타앙코르(MetaEncore Co., Ltd). Rim J. brings experience from previous roles at Veri-fun, SEMIFIVE, SemiFive and Synopsys Inc. Rim J. holds a 1992 - 1994 Master of Engineering in Electronics @ Ajou University. With a robust skill set that includes Timing Closure, Specman, TCL, VHDL, RTL design and more. Rim J. has 1 emails and 1 mobile phone numbers on RocketReach.
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