Riley M. Email
Principal Formal Verification Engineer @ Ampere
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Riley M. Location
- Portland, OR, US
Riley M. Work
- Principal Formal Verification Engineer @ (March 2026 - Present)
- Senior Formal Verification Engineer @ (March 2025 - March 2026)
- Formal Verification Engineer @ (December 2023 - March 2025)
- CPU Formal Verification Engineer @ (January 2022 - December 2023)
- FPGA Validation Engineer Intern @ (June 2021 - December 2021)
- Advanced Clinical Associate @ (January 2020 - May 2021)
- Member @ (October 2019 - September 2020)
- Student Innovator - Finalist @ (April 2019 - June 2019)
- Emergency Department Scribe @ (January 2018 - May 2019)
Riley M. Education
- Portland State University
Master of Science - MS (Electrical and Electronics Engineering)
2020-2021 - University of Portland
Bachelor of Science - BS (Biochemistry)
2016-2019
Riley M. Skills
- CAD
- Data Analysis
- Invention
- Matlab
- Microsoft Office
- Microsoft PowerPoint
- Printed Circuit Board (PCB) Design
- Product Development
- QuestaSim
- SystemVerilog
Riley M. Summary
- Riley M., based in Portland, OR, US, is currently a Principal Formal Verification Engineer at Ampere. Riley M. brings experience from previous roles at Ampere and Intel Corporation. Riley M. holds a 2020 - 2021 Master of Science - MS in Electrical and Electronics Engineering @ Portland State University. With a robust skill set that includes CAD, Data Analysis, Invention, Matlab, Microsoft Office and more. Riley M. has 1 emails on RocketReach.
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