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Rathna M. Location
Hillsboro, OR, US
Rathna M. Work
SoC Design Engineer @ (April 2013 - Present)
Student Worker - Under System Analyst, Department of Physics @ (September 2010 - September 2012)
Rathna M. Education
University of Cincinnati
M.S (Computer Engineering)
2010-2012
Anna University Chennai
BE (Electronics and Communication Engineering)
2005-2009
Rathna M. Skills
Verilog
Design Compiler
Primetime
VCS
Formality
Hspice
Magic
C++
Perl
Magic Layout Tool
SPICE
Veritas Cluster Server
Compilers
VHDL
Subversion
Apache
Semiconductors
Design
SoC
Rathna M. Summary
Rathna M., based in Hillsboro, OR, US, is currently a SoC Design Engineer at Intel Corporation. Rathna M. brings experience from previous roles at University of Cincinnati. Rathna M. holds a 2010 - 2012 M.S in Computer Engineering @ University of Cincinnati. With a robust skill set that includes Verilog, Design Compiler, Primetime, VCS, Formality and more. Rathna M. has 4 emails and 1 mobile phone numbers on RocketReach.
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