Randall Paul's Location
San Jose, CA, US
Randall Paul's Work
- Senior Staff Design Engineer @ Western Digital
- Senior High Speed Digital Design Engineer @ Micron Technology
- Design Engineer IV @ Quantum
- ASiC Design Engineer @ Emulex, an Avago Technologies Company
- Design Engineer @ Seagate Corporation
- Design Engineer @ Integral Peripherals Corporation
- Design Engineer @ IPT, Incorporated
- Design Engineer @ Unisys Peripherals Group
- Design Engineer @ Helios, Incorporated
Randall Paul's Education
- Carnegie Mellon University
B.S (Electrical Engineering)
1983 - 1987 - Tower Hill School
High School Diploma (General)
1979 - 1983
Randall Paul's Skills
- Low-power Design
- GPS
- GSM
- MEMS
- RFID+
- ARM Cortex-M3
- Signal Integrity
- FPGA
- Circuit Design
- PCB design
Randall Paul's Summary
Randall Paul, based in San Jose, CA, US, is currently a Senior Staff Design Engineer at Western Digital, bringing experience from previous roles at Micron Technology, Quantum, Emulex and Seagate Corporation. Randall Paul holds a 1983 - 1987 B.S in Electrical Engineering @ Carnegie Mellon University. With a robust skill set that includes Low-power Design, GPS, GSM, MEMS, RFID+ and more, Randall Paul contributes valuable insights to the industry. Randall Paul has 2 emails and 1 mobile phone number on RocketReach.
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