Ran Levy Email
Senior ASIC Engineer @ Sony Semicon (IL)
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Ran Levy Location
- Israel
Ran Levy Work
- senior ASIC Engineer @ (September 2015 - Present)
- senior ASIC Engineer @ (April 2011 - September 2015)
- senior ASIC and FPGA Engineer @ (May 2004 - April 2011)
- FPGA Engineer @ (April 2003 - April 2004)
- ASIC Engineer @ (January 2000 - March 2003)
- A member of an R and D team @ Ministry of Defense, R&D Unit (January 1993 - January 1998)
Ran Levy Education
- Recanati Business School - Tel Aviv University
MSc (in Management Sciences)
2006-2008 - Ben-Gurion University of the Negev
BSc (Electrical and Computer Engineering)
1997-2001 - Ort Singalovsky
Practical Engineer
1990-1992
Ran Levy Skills
- Verilog
- Xilinx
- FPGA
- Altera
- SystemVerilog
- ModelSim
- RTL design
- ASIC
- RTL coding
- Quartus
- Specman
- CPLD
- SoC
- VLSI
- Logic Design
- Altera Quartus
- VCS
- Debugging
- IC
- Architecture
- AHB
- IP
- Hardware Design
- Simulation
- Digital Design
- High Speed Design
- IP design
- IPv6
- Infiniband
- Ethernet
- Ethereal
- TCP/IP
- TCP/UDP
- IXIA
- ARM
- Integration
- Fast Ethernet
- Spyglass
- BIST
- Data Synchronization
- IPv4
- I2C
- WEP
- WPA
- MAC
- Networking
- Perl
- Unix
- System Architecture
- VLAN
Ran Levy Summary
- Ran Levy, based in Israel, is currently a senior ASIC Engineer at Sony (Altair Semiconductor). Ran Levy brings experience from previous roles at Marvell Israel Ltd., Mellanox Technologies (Voltaire), Extricom and AMCC. Ran Levy holds a 2006 - 2008 MSc in in Management Sciences @ Recanati Business School - Tel Aviv University. With a robust skill set that includes Verilog, Xilinx, FPGA, Altera, SystemVerilog and more. Ran Levy has 1 emails on RocketReach.
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