Ramya G Email

Ramya G Skills

• Verilog
• system verilog
• Modelsim and ISE
• ASIC/FPGA Design Flow, Digital Design methodologies
• Perl scripting
• RTL Coding, FSM based design, Simulation,
• Coverage Driven Verification
• ModelSim
• Perl
• SystemVerilog
• ASIC
• RTL design
• VLSI
• RTL coding
• Open Verification Methodology
• Logic Design
• TCL
• SoC
• EDA
• Functional Verification
• Digital Electronics
• Simulations
• Static Timing Analysis
• Formal Verification
• Application-Specific Integrated Circuits (ASIC)
• Very-Large-Scale Integration (VLSI)