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Ramesh Sharma Location
San Jose, CA, US
Ramesh Sharma Work
Principal Engineer @ (January 2018 - Present)
Principal Engineer @ (January 2016 - January 2018)
Engineering Manager @ (January 2013 - December 2015)
Engineering Manager @ (March 2009 - December 2012)
Senior Staff CAD Engineer @ (January 2007 - April 2009)
Staff CAD Engineer @ (January 2004 - December 2006)
Senior CAD Engineer @ (June 1999 - December 2003)
Member of Technical Staff @ (January 1998 - May 1999)
Design Engineer @ (August 1996 - December 1997)
Ramesh Sharma Education
Santa Clara University
National Institute of Technology Hamirpur-Alumni
Ramesh Sharma Skills
Verilog
VLSI
ASIC
TCL
DFT
SoC
Semiconductors
EDA
Static Timing Analysis
Computer Architecture
Debugging
Perl
C++
Algorithms
Project Management
Agile Methodologies
ATPG
Scan
Software Design
Computer Hardware
Public Speaking
AutoCAD
Engineering
Java
SQL
Management
Research
System on a Chip Soc
RTL design
Microprocessors
Processors
Intel
Testing
Application Specific Integrated Circuits Asic
FPGA
SystemVerilog
Very Large Scale Integration Vlsi
System on a Chip
Very Large Scale Integration
Application Specific Integrated Circuits
Ramesh Sharma Summary
Ramesh Sharma, based in San Jose, CA, US, is currently a Principal Engineer at Intel Corporation. Ramesh Sharma brings experience from previous roles at Intel Corporation. Ramesh Sharma holds a Santa Clara University. With a robust skill set that includes Verilog, VLSI, ASIC, TCL, DFT and more. Ramesh Sharma has 5 emails and 3 mobile phone numbers on RocketReach.
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