Ramesh Dandapani's Location

Cupertino, CA, US

Ramesh Dandapani's Work

  • Senior Manager Hardware Design @ Sage
  • Design and Development Manager - Multimedia Group @ Tata Elxsi
  • Project Lead Engineer @ Tata Elxsi
  • Design Engineer - Minicomputer Lab @ Samsung India
  • Senior Hardware Engineer @ U&I Software
  • Project Lead Engineer, Hardware @ Aparajitha Technologies
  • Hardware and Firmware Design Engineer @ HCL America, Inc.

Ramesh Dandapani's Education

  • College of Engineering, Guindy

    Master of Engineering (M.Eng.) (Electrical, Electronics and Communications Engineering)

    1986 - 1988
  • Karnatak University

    Bachelor of Engineering (B.E.) (Electrical, Electronics and Communications Engineering)

    1980 - 1984

Ramesh Dandapani's Skills

  • IC
  • Video
  • Analog
  • Digital Signal Processors
  • Chip Architecture
  • Firmware
  • Hardware Architecture
  • System Architecture
  • Algorithms
  • SoC

Ramesh Dandapani's Summary

Ramesh Dandapani, based in Cupertino, CA, US, is currently a Senior Architect, IC and System Design at MegaChips Technology America Corporation, bringing experience from previous roles at STMicroelectronics, Genesis Microchip, Sage Inc and Tata Elxsi. Ramesh Dandapani holds a 1986 - 1988 Master of Engineering (M.Eng.) in Electrical, Electronics and Communications Engineering @ College of Engineering, Guindy. With a robust skill set that includes IC, Video, Analog, Digital Signal Processors, Chip Architecture and more, Ramesh Dandapani contributes valuable insights to the industry. Ramesh Dandapani has 5 emails and 1 mobile phone number on RocketReach.

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