CPU IP Verification Engineer Consultant @ (August 2021 - August 2024)
IP and SOC Design Verification Engineer @ (January 2021 - August 2021)
Assistant System Engineer @ (October 2018 - October 2019)
Ramees M Education
Maven silicon Bangalore 2019-2020
TKM College of Engineering , Kollam 2014-2018
Chinmaya Vidyalaya taliparamba 2006-2013
Ramees M Skills
Emulator
Python (Programming Language)
Fault injection
Dual Core Lock Step Protection
FuSa
RTL Coding
VERDI
Regression Testing
Shell Scripting
ARM Assembly
ARM Architecture
System on a Chip (SoC)
Universal Verification Methodology (UVM)
SystemVerilog
Assertion Based Verification
Application-Specific Integrated Circuits (ASIC)
Digital Electronics
Very-Large-Scale Integration (VLSI)
Field-Programmable Gate Arrays (FPGA)
Object-Oriented Programming (OOP)
Agile Methodologies
Scrum
Verilog
Perl
QuestaSim
Git
Linux
Matlab
Java
C (Programming Language)
Arduino IDE
JavaScript
ABV
Functional Verification
AMBA AHB
AHB
APB
Code Coverage
RTL Design
Static Timing Analysis
DPI
Digital Designs
FSM
Xilinx ISE
Logic Synthesis
Cadence
Bluetooth Low Energy
AXI
DFT
RAL
I2C
Ramees M Summary
Ramees M, based in Bengaluru, KA, IN, is currently a Senior Design Verification Engineer Consultant at AMD. Ramees M brings experience from previous roles at Arm, Incise Infotech Private Limited and Tata Consultancy Services. Ramees M holds a 2019 - 2020 Maven silicon Bangalore. With a robust skill set that includes Emulator, Python (Programming Language), Fault injection, Dual Core Lock Step Protection, FuSa and more. Ramees M has 3 emails on RocketReach.
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