Ramees M Email
Senior Design Verification Engineer Consultant @ AMD
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Ramees M Location
- Bengaluru, KA, IN
Ramees M Work
- 2025 -now Senior Design Verification Engineer Consultant @
- 2021 -2024 CPU IP Verification Engineer Consultant @
- 2021 -2021 IP and SOC Design Verification Engineer @
- 2018 -2019 Assistant System Engineer @
Ramees M Education
- Maven silicon Bangalore 2019-2020
- TKM College of Engineering , Kollam 2014-2018
- Chinmaya Vidyalaya taliparamba 2006-2013
Ramees M Skills
- Emulator
- Python (Programming Language)
- Fault injection
- Dual Core Lock Step Protection
- FuSa
- RTL Coding
- VERDI
- Regression Testing
- Shell Scripting
- ARM Assembly
- ARM Architecture
- System on a Chip (SoC)
- Universal Verification Methodology (UVM)
- SystemVerilog
- Assertion Based Verification
- Application-Specific Integrated Circuits (ASIC)
- Digital Electronics
- Very-Large-Scale Integration (VLSI)
- Field-Programmable Gate Arrays (FPGA)
- Object-Oriented Programming (OOP)
- Agile Methodologies
- Scrum
- Verilog
- Perl
- QuestaSim
- Git
- Linux
- Matlab
- Java
- C (Programming Language)
- Arduino IDE
- JavaScript
- ABV
- Functional Verification
- AMBA AHB
- AHB
- APB
- Code Coverage
- RTL Design
- Static Timing Analysis
- DPI
- Digital Designs
- FSM
- Xilinx ISE
- Logic Synthesis
- Cadence
- Bluetooth Low Energy
- AXI
- DFT
- RAL
- I2C
Ramees M Summary
- Ramees M, based in Bengaluru, KA, IN, is currently a Senior Design Verification Engineer Consultant at AMD. Ramees M brings experience from previous roles at Arm, Incise Infotech Private Limited and Tata Consultancy Services. Ramees M holds a 2019 - 2020 Maven silicon Bangalore. With a robust skill set that includes Emulator, Python (Programming Language), Fault injection, Dual Core Lock Step Protection, FuSa and more. Ramees M has 1 emails on RocketReach.
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