Rakesh M Email
ASIC Design Engineer @ Meta
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Rakesh M Location
- Sunnyvale, CA, US
Rakesh M Work
- 2024 -now ASIC Design Engineer @
- 2022 -2024 ASIC Design Engineer @
- 2020 -2022 Digital Design Manager @
- 2016 -2022 Digital Design Engineer @
- 2014 -2016 Engineer, Staff 1 - IC Design @
- 2012 -2014 Engineer, IC Design @
- 2011 -2011 Summer Intern @
Rakesh M Education
- National Institute of Technology Karnataka, Surathkal
Bachelor of Technology (B.Tech.) (Electronics and Communications Engineering)
2008-2012
Rakesh M Skills
- RTL Coding
- Low-power Design
- C (Programming Language)
- RTL Design
- system verilog
- Graphics
- Verilog
- SystemVerilog
- VHDL
- UVM
- Python
- Formal Verification
- ASIC
- Spyglass
- VLSI
- PCIe
- SoC Design
- UPF
- CPF
- C
- UART
- I2C
- SPI
- Perl
- Linux
- Open Verification Methodology
- Awk
- System on a Chip (SoC)
- Integrated Circuit Design
- Functional Verification
- Application-Specific Integrated Circuits (ASIC)
- Very-Large-Scale Integration (VLSI)
- Open Verification
- System On A Chip Soc
- NFC
- Digital Design
- Software
- Assertion Based
- Application Specific Integrated Circuits Asic
- C++
- Palladium
- Design
- Assertion Based Verification
- Very Large Scale Integration Vlsi
- Architecture
Rakesh M Summary
- Rakesh M, based in Sunnyvale, CA, US, is currently a ASIC Design Engineer at Meta. Rakesh M brings experience from previous roles at Meta, Texas Instruments and Broadcom. Rakesh M holds a 2008 - 2012 Bachelor of Technology (B.Tech.) in Electronics and Communications Engineering @ National Institute of Technology Karnataka, Surathkal. With a robust skill set that includes RTL Coding, Low-power Design, C (Programming Language), RTL Design, system verilog and more. Rakesh M has 3 emails on RocketReach.
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