Rajesh Singh Email
Design Engineer @ Pacific Digital
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Rajesh Singh Location
- Costa Mesa, CA, US
Rajesh Singh Work
- 2003 -now Design Engineer @
- 2002 -2002 Design Engineer @ Terago Communications
- 1998 -2002 Design Engineer @
- 1989 -1993 Design Engineer @ Digital Electronics
Rajesh Singh Education
- University of Mumbai
Bachelor Of Science (Biology, Electronics)
1986-1989
Rajesh Singh Skills
- Verilog
- Integrated Circuit Design
- Timing Closure
- SoC
- RTL design
- Simulations
- C
- EDA
- Logic Synthesis
- ASIC
- System Architecture
- Systems Design
- Semiconductors
- FPGA
- Embedded Systems
Rajesh Singh Summary
- Rajesh Singh, based in Costa Mesa, CA, US, is currently a Design Engineer at Pacific Digital. Rajesh Singh brings experience from previous roles at Terago Communications, Lsi, an Avago Technologies Company and Digital Electronics. Rajesh Singh holds a 1986 - 1989 Bachelor Of Science in Biology, Electronics @ University of Mumbai. With a robust skill set that includes Verilog, Integrated Circuit Design, Timing Closure, SoC, RTL design and more. Rajesh Singh has 1 emails on RocketReach.
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