Rajesh Rajput Email & Phone Number
Senior EDA Engineer @ Intel Corporation
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Rajesh Rajput Location
- Folsom, CA, US
Rajesh Rajput Work
- now Senior EDA Engineer @
- 2006 -2009 Core Comp Technical Leader @
- 2004 -2006 Senior EDA Coordinator @
- 2001 -2004 Senior EDA Engineer @
- 1999 -2001 Senior PDK Developer @
- 1996 -1999 CAD Engineer @
Rajesh Rajput Education
- Oregon Health & Science University
MSEE (Electrical Engineering)
1994-1996
Rajesh Rajput Skills
- EDA
- Parasitic Extraction
- Physical Design
- LVS
- Cadence
- Physical Verification
- Analog
- Analog Circuit Design
- DRC
- Mixed Signal
- Semiconductors
- Spectre
- ASIC
- Layout Versus Schematic (LVS)
- Cadence Spectre
- Design Rule Checking (DRC)
- Application-Specific Integrated Circuits (ASIC)
- Integrated Circuits (IC)
- Simulations
- System on a Chip (SoC)
- Layout Versus Schematic Lvs
- System On A Chip Soc
- Sales
- Intel
- Consultation
- Design Rule Checking Drc
- Support
- Integrated Circuits Ic
- Application Specific Integrated Circuits Asic
- Training
- C++
- Customer Support
- Technical Support
- Project Management
- Technician
- Layout Versus Schematic
- Design Rule Checking
- Application Specific Integrated Circuits
- Integrated Circuits
- System on a Chip
Rajesh Rajput Summary
- Rajesh Rajput, based in Folsom, CA, US, is currently a Senior EDA Engineer at Intel Corporation. Rajesh Rajput brings experience from previous roles at Cadence Design Systems and Texas Instruments. Rajesh Rajput holds a 1994 - 1996 MSEE in Electrical Engineering @ Oregon Health & Science University. With a robust skill set that includes EDA, Parasitic Extraction, Physical Design, LVS, Cadence and more. Rajesh Rajput has 5 emails and 2 mobile phone numbers on RocketReach.
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