Rajeev P Email
SoC Design @ Intel Corporation
5 free lookup(s). No credit card required.
If you need more lookups,
subscriptions start at $34 USD/month.
Rajeev P Location
- Hyderabad, IN
Rajeev P Work
- 2018 -now SoC Design @
- 2016 -2018 Lead Engineer @
- 2013 -2016 Senior Design Engineer @
- 2011 -2012 Logic Design Engineer @
- 2008 -2011 Design Engineer @
Rajeev P Education
- Chaitanya Bharathi Institute Of Technology
B.E (ELECTRONICS AND COMMUNICATION)
2004-2008
Rajeev P Skills
- Logic Design
- RTL design
- ASIC
- Functional Verification
- AMBA AHB
- Microcontrollers
- Verilog
- Static Timing Analysis
- ModelSim
- VHDL
- FPGA
- EDA
- C
- Timing Closure
- Microprocessors
- RTL coding
- Debugging
- Logic Synthesis
Rajeev P Summary
- Rajeev P, based in Hyderabad, IN, is currently a SoC Design at Intel Corporation. Rajeev P brings experience from previous roles at Qualcomm, AMD, IBM and Tata Elxsi. Rajeev P holds a 2004 - 2008 B.E in ELECTRONICS AND COMMUNICATION @ Chaitanya Bharathi Institute Of Technology. With a robust skill set that includes Logic Design, RTL design, ASIC, Functional Verification, AMBA AHB and more. Rajeev P has 3 emails on RocketReach.
Looking for a different Rajeev P?
Find contact details for 700 million professionals.
G2 Crowd Trusted
300K+ Plugin Users
© 2026 RocketReach.co