Rajeev P Email
SoC Design @ Intel Corporation
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Rajeev P Location
- Hyderabad, IN
Rajeev P Work
- SoC Design @ (July 2018 - Present)
- Lead Engineer @ (November 2016 - July 2018)
- Senior Design Engineer @ (October 2013 - October 2016)
- Logic Design Engineer @ (June 2011 - October 2012)
- Design Engineer @ (November 2008 - May 2011)
Rajeev P Education
- Chaitanya Bharathi Institute Of Technology
B.E (ELECTRONICS AND COMMUNICATION)
2004-2008
Rajeev P Skills
- Logic Design
- RTL design
- ASIC
- Functional Verification
- AMBA AHB
- Microcontrollers
- Verilog
- Static Timing Analysis
- ModelSim
- VHDL
- FPGA
- EDA
- C
- Timing Closure
- Microprocessors
- RTL coding
- Debugging
- Logic Synthesis
Rajeev P Summary
- Rajeev P, based in Hyderabad, IN, is currently a SoC Design at Intel Corporation. Rajeev P brings experience from previous roles at Qualcomm, AMD, IBM and Tata Elxsi. Rajeev P holds a 2004 - 2008 B.E in ELECTRONICS AND COMMUNICATION @ Chaitanya Bharathi Institute Of Technology. With a robust skill set that includes Logic Design, RTL design, ASIC, Functional Verification, AMBA AHB and more. Rajeev P has 3 emails on RocketReach.
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