Vice President Of Engineering @ (August 2020 - February 2021)
Team Lead and Sr. Designer @ (September 2018 - August 2020)
Principal Design Engineer @ (June 2007 - August 2018)
Sr. Design Engineer @ (April 2006 - June 2007)
Sr. Design Engg (Mixed Signal ICs) @ (January 2001 - April 2006)
Sr Analog IC Design Engineer @ Infineon Technologies (January 1997 - January 2000)
Project Scientist @ Indian Institute of Technology, New Delhi (October 1995 - June 1997)
Rajeev Govil Education
University of California, Santa Cruz
(Certificate Course in Engineering Management)
2009
AMU, Aligarh, India
B.S (Electrical Engineering)
UC Santa Barbara
(Short course on Modern Infrared Detectors & System Applications)
Rajeev Govil Skills
Low-power Design
Analog Circuit Design
Mixed Signal
ASIC
Analog
FPGA
EDA
Integrated Circuit Design
CMOS
IC
RTL design
Electronics
SoC
Verilog
Digital Signal Processors
Circuit Design
VLSI
Hardware Architecture
Semiconductors
Integrated Circuits (IC)
Tiger Kidnap Specialist
Integrated Circuit
Post Incident Reviews and Normalisation Strategies
Crisis Management Training and Testing
Low Power Design
Research
Integrated Circuits Ic
Policy Reviews
Management
Graphic Design
Digital Signal
Integrated Circuits
Rajeev Govil Summary
Rajeev Govil, based in California, United States, is currently a Engineering Director - Programs and Projects at Claros. Rajeev Govil brings experience from previous roles at Epirus, SeeDevice Inc., FLIR Systems, Inc and ON Semiconductor. Rajeev Govil holds a University of California, Santa Cruz. With a robust skill set that includes Low-power Design, Analog Circuit Design, Mixed Signal, ASIC, Analog and more. Rajeev Govil has 3 emails and 4 mobile phone numbers on RocketReach.
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