Rajan P Email

Rajan P Email

DFT Engineer @ Qualcomm

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Rajan P Location

Chennai, TN, IN

Rajan P Work

  • 2021 - now  DFT Engineer @ Qualcomm
  • 2019 - 2021 DFT Engineer @ HCL Axon technologies
  • 2018 - 2021 DFT engineer for Intel @ HCL America, Inc.
  • 2019 - 2019 HCL @ HCL America, Inc.
  • 2014 - 2018 Post silicon validation engineer for Qualcomm processors and Modem @ Tessolve Semiconductor Pvt. Ltd.

Rajan P Education

  • Kamaraj College of Engineering and Technology

    Bachelor of Engineering - BE (Electrical, Electronics and Communications Engineering)

Rajan P Skills

  • Boundary Scan
  • Scan Insertion
  • Scan
  • DFD RTL Validation
  • Memory Validation
  • DFT RTL Validation
  • Automatic Test Pattern Generation
  • Design for Debug
  • Perl
  • Bscan Insertion

Rajan P Summary

Rajan P, based in Chennai, TN, IN, is currently a DFT Engineer at Qualcomm. Rajan P brings experience from previous roles at HCL Axon technologies, HCL Technologies and Tessolve Semiconductor Pvt. Ltd.. Rajan P holds a Bachelor of Engineering - BE in Electrical, Electronics and Communications Engineering @ Kamaraj College of Engineering and Technology. With a robust skill set that includes Boundary Scan, Scan Insertion, Scan, DFD RTL Validation, Memory Validation and more. Rajan P has 1 emails on RocketReach.
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