Senior Design Manager @ (December 2006 - August 2010)
ASIC Design Lead @ (December 2005 - November 2006)
CPU Design @ (November 2000 - November 2005)
Application Engineer @ (December 1999 - October 2000)
Raj Mareps Education
MSU
MS
Raj Mareps Skills
EDA
Semiconductors
ASIC
VLSI
Integrated Circuit Design
IC
Physical Design
SoC
Static Timing Analysis
Semiconductor Industry
Embedded Systems
Perl
Computer Architecture
Simulations
Integration
Application-Specific Integrated Circuits (ASIC)
System on a Chip (SoC)
Application Specific Integrated Circuits Asic
System On A Chip Soc
Application Specific Integrated Circuits
System on a Chip
Raj Mareps Summary
Raj Mareps, based in Cupertino, CA, US, is currently a Founding Member at Tsavorite Scalable Intelligence. Raj Mareps brings experience from previous roles at Intel Corporation. Raj Mareps holds a MS @ MSU. With a robust skill set that includes EDA, Semiconductors, ASIC, VLSI, Integrated Circuit Design and more. Raj Mareps has 4 emails and 2 mobile phone numbers on RocketReach.
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