Rainer Ulrich Email
PMTS Design Engineer @ AMD
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Rainer Ulrich Location
- Cambridge, Cambridgeshire, United Kingdom
Rainer Ulrich Work
- PMTS Design Engineer @ (November 2022 - Present)
- Senior Verification Manager @ (January 2021 - November 2022)
- Senior Manager, Verification @ (October 2020 - January 2021)
- Head Of Verification @ UltraSoC (October 2017 - October 2020)
- Principal Engineer @ UltraSoC (October 2014 - October 2017)
- Senior Principal Engineer @ (April 2013 - August 2014)
- Principal Engineer @ (July 2007 - April 2013)
- Senior Engineer @ (September 2004 - July 2007)
- Engineer @ Alphamosaic Ltd (March 2002 - September 2004)
- Engineer @ (February 1991 - February 2002)
Rainer Ulrich Education
- University of Stuttgart
Rainer Ulrich Skills
- ASIC
- IC
- SoC
- Verilog
- RTL design
- Debugging
- FPGA
- Semiconductors
- Static Timing Analysis
- SystemVerilog
- VLSI
- Functional Verification
- EDA
- Integrated Circuit Design
- UVM
- DFT
- Low-power Design
- Logic Synthesis
- Leadership
- System On A Chip Soc
- Strategy
- Integrated Circuit
- Integrated Circuits Ic
- Testing
- Application Specific Integrated Circuits Asic
- Project Management
- Low Power Design
- Application Specific Integrated Circuits
- Integrated Circuits
- System on a Chip
Rainer Ulrich Summary
- Rainer Ulrich, based in Cambridge, Cambridgeshire, United Kingdom, is currently a PMTS Design Engineer at AMD. Rainer Ulrich brings experience from previous roles at Siemens Digital Industries Software, Mentor Graphics and UltraSoC. Rainer Ulrich holds a University of Stuttgart. With a robust skill set that includes ASIC, IC, SoC, Verilog, RTL design and more. Rainer Ulrich has 2 emails on RocketReach.
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