Quan Lin Email & Phone Number
ASIC Design Architect @ Kwai Inc.
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Quan Lin Location
- San Jose, CA, US
Quan Lin Work
- 2020 -now ASIC Design Architect @
- 2016 -2020 Design Lead @
- 2005 -2016 Senior Staff Design Engineer @
- 2001 -2005 Senior Digital Design Engineer @
Quan Lin Education
- University of Rochester
Master of Science (M.S.) (Electrical and Electronics Engineering)
1999-2001 - Tsinghua University
Master of Engineering (Electronic Engineering)
1996-1999 - Tsinghua University
Bachelor of Engineering (B.E.) (Electronic Engineerin)
1991-1996
Quan Lin Skills
- High Speed Phy
- Logic
- Logic Design
- C/C++
- Field Programmable Gate Arrays Fpga
- Prime Time
- Debugging
- Perl
- RTL design
- Matlab
- PCIe
- Languages
- ASIC
- SATA
- Altera Stratix/Apexxilinx Virtex 6
- Asic Design Tools
- Verilog
- Integrated Circuit Design
- USB
- Xilinx
- Formality
- Gbe
- High Speed Phy Interfaces
- Embedded Systems
- Application Specific Integrated Circuits Asic
- FPGA
- SoC
- RTL coding
- VCS
- Fpga Tools
- Altera
- Hdmi/Usb/Pcie Protocol Analyzer
- Semiconductors
- Static Timing Analysis
- Logic Analyzer
- Lab Tools
- Design Compiler
- Verdi
- Application Specific Integrated Circuits
- Field Programmable Gate Arrays
Quan Lin Summary
- Quan Lin, based in San Jose, CA, US, is currently a ASIC Design Architect at Kuaishou Technology. Quan Lin brings experience from previous roles at Intel Corporation, Marvell Semiconductor and Chrontel. Quan Lin holds a 1999 - 2001 Master of Science (M.S.) in Electrical and Electronics Engineering @ University of Rochester. With a robust skill set that includes High Speed Phy, Logic, Logic Design, C/C++, Field Programmable Gate Arrays Fpga and more. Quan Lin has 3 emails on RocketReach.
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