Qadeer Khan's Location
India
Qadeer Khan's Work
- Assistant Professor @ Indian Institute of Technology, Madras
- Visiting Assistant Professor @ Indian Institute of Technology, Madras
- Staff Engineer, PMIC Systems @ Qualcomm
- Staff Engineer @ Qualcomm
- Graduate Research Assistant @ Oregon State University
- IC Design Intern @ National Semiconductor
- Design Intern @ National Semiconductor
- Design Intern @ National Semiconductor
- Engineering Lead @ Siways Microelectroncis Pvt. Ltd.
- Sr. Design Engineer @ NXP acquires Freescale Semiconductor
Qadeer Khan's Education
- Oregon State University
PhD
2007 - 2012 - Jamia Millia Islamia
B.Tech
1995 - 1999
Qadeer Khan's Skills
- VLSI
- IC
- Team Leadership
- PLL
- Power Management
- Mixed Signal
- Analog
- Analog Circuit Design
- ASIC
- Integrated Circuit Design
Qadeer Khan's Summary
Qadeer Khan, based in India, is currently a Assistant Professor at Indian Institute of Technology, Madras, bringing experience from previous roles at Indian Institute of Technology, Madras, Qualcomm and Oregon State University. Qadeer Khan holds a 2007 - 2012 PhD @ Oregon State University. With a robust skill set that includes VLSI, IC, Team Leadership, PLL, Power Management and more, Qadeer Khan contributes valuable insights to the industry. Qadeer Khan has 3 emails and 1 mobile phone number on RocketReach.
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