Pushkar P Email
Memory Silicon Validation @ Google
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Pushkar P Location
- San Jose, CA, US
Pushkar P Work
- 2022 -now Memory Silicon Validation @
- 2017 -2022 Post-Silicon Validation @
- 2014 -2017 Sr. Product Engineering Manager - DDR IP @
- 2014 -2014 Staff Corporate Applications Engineer - DDR Phy @
- 2009 -2014 Staff ASIC Engineer @
- 2008 -2009 Design Verification Engineer @
- 2007 -2008 ASIC Engineer @ ServerEngines
- 2006 -2007 Design Verification Engineer @ Somarouthu Technologies
- 2002 -2006 Owner @
Pushkar P Education
- Victoria University
Master of Science (M.S) (Computer systems)
2004-2005 - Victoria University
Master of Science (M.S) (Microelectronics)
2003-2005 - BNCOE
Bachelor of Engineering (B.E.) (Electrical and Electronics Engineering)
1998-2002
Pushkar P Skills
- RTL design
- EDA
- Marketing
- Semiconductors
- Static Timing Analysis
- Sdram
- Logic Design
- TCL
- SQL
- SystemVerilog
- Customer Support
- Logic Synthesis
- Debugging
- Ddr Phy Ip
- VHDL
- Java
- Memory Interfaces
- Perl
- Timing Closure
- Synopsys Primetime
- ASIC
- System on a Chip Soc
- Synopsys tools
- Graphic Design
- SoC
- Business Analysis
- Floorplanning
- Synopsys Design Compiler
- Verilog
- Design Integration
- Field Programmable Gate Arrays Fpga
- Silicon Power Om
- High Speed Interfaces
- ARM
- Silicon Validation
- C++
- C#
Pushkar P Summary
- Pushkar P, based in San Jose, CA, US, is currently a Memory Silicon Validation at Google. Pushkar P brings experience from previous roles at Intel Corporation, Cadence Design Systems, Synopsys Inc and LSI Corporation. Pushkar P holds a 2004 - 2005 Master of Science (M.S) in Computer systems @ Victoria University. With a robust skill set that includes RTL design, EDA, Marketing, Semiconductors, Static Timing Analysis and more. Pushkar P has 3 emails on RocketReach.
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