Priya Joshi Email & Phone Number
SOC Design Engineer @ Intel Corporation
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Priya Joshi Location
- Santa Clara, CA, US
Priya Joshi Work
- SOC Design Engineer @ (June 2020 - Present)
- IP design Intern @ (August 2019 - December 2019)
- SOC Design Intern @ (May 2019 - August 2019)
- Intern @ ATC Labs (July 2017 - June 2018)
- Intern @ (June 2016 - July 2016)
- Intern @ ATC Labs (June 2015 - July 2015)
Priya Joshi Education
- Texas A&M University
Master of Science - MS (Computer Engineering)
2018-2020 - G.B. Pant Govt. Engineering College
Bachelor of Technology - BTech (Electrical, Electronics and Communications Engineering)
2013-2017
Priya Joshi Skills
- ARM Cortex-M
- Antenna Measurements
- Antennas
- C++
- C,C++
- Computer Architecture
- DV
- Embedded C
- Embedded Systems
- FPGA
- FPGA design
- Functional Verification
- IE3D- EM simulation software
- Internet Protocol (IP)
- Leadership
- Logic Design
- MATLAB
- Microsoft Excel
- Microsoft PowerPoint
- Microsoft Word
- PSpice
- Python
- System Verilog
- Universal Verification Methodology (UVM)
- VHDL
- VLSI
- Verilog
- Xilinx ISE
- Xilinx Vivado Design Suite
Priya Joshi Summary
- Priya Joshi, based in Santa Clara, CA, US, is currently a SOC Design Engineer at Intel Corporation. Priya Joshi brings experience from previous roles at Intel Corporation, ATC Labs and Avery Weigh-Tronix. Priya Joshi holds a 2018 - 2020 Master of Science - MS in Computer Engineering @ Texas A&M University. With a robust skill set that includes ARM Cortex-M, Antenna Measurements, Antennas, C++, C,C++ and more. Priya Joshi has 5 emails and 4 mobile phone numbers on RocketReach.
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