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Pragya Laad Location
Bengaluru, KA, IN
Pragya Laad Work
Senior Principal Engineer @ (August 2025 - Present)
Principal Design Engineer @ (April 2021 - Present)
Staff Design Engineer @ (April 2018 - April 2021)
Senior Design Engineer @ (April 2014 - March 2018)
Technical Lead @ (June 2008 - March 2014)
MTS-TQE @ Persistent Systems Pvt. Ltd. (January 2005 - January 2006)
Pragya Laad Education
Birla Institute of Technology and Science, Pilani 2006-2008
Pragya Laad Skills
VLSI
ASIC
Semiconductors
RTL design
Static Timing Analysis
Physical Design
Verilog
SoC
Physical Verification
System on a Chip (SoC)
Very-Large-Scale Integration (VLSI)
Application-Specific Integrated Circuits (ASIC)
EDA
Logic Synthesis
Linux
Perl
Pragya Laad Summary
Pragya Laad, based in Bengaluru, KA, IN, is currently a Senior Principal Engineer at Cadence Design Systems (India) Pvt. Ltd.. Pragya Laad brings experience from previous roles at Arm and NXP Semiconductors. Pragya Laad holds a 2006 - 2008 Birla Institute of Technology and Science, Pilani. With a robust skill set that includes VLSI, ASIC, Semiconductors, RTL design, Static Timing Analysis and more. Pragya Laad has 3 emails and 1 mobile phone numbers on RocketReach.
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