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Prabal Mallick Location
Bhubaneswar, OD, IN
Prabal Mallick Work
Principal Engineer @ (August 2021 - Present)
Member Technical Staff @ (January 2017 - March 2018)
PCIe 3.0 and USB 3.0 Physical Layer RTL IP development as Senior Staff Engineer @ (May 2014 - December 2016)
802.11n Physical Layer RTL IP development as Lead Engineer @ (January 2011 - April 2014)
Development of 802.11n MAC layer as Lead Engineer @ (April 2010 - December 2010)
Verification of PCIe as Lead Engineer @ (October 2009 - April 2010)
HomePlug AV Physical Layer RTL IP development as Lead Engineer @ (March 2007 - September 2009)
SDIO IP verification as Senior Engineer @ (November 2006 - February 2007)
Development of IEEE802.11n baseband algorithms as Senior Engineer @ (June 2006 - September 2006)
Development of generic OFDM system as Senior Engineer @ (January 2006 - June 2006)
Development of DVBS and DSS Baseband Receiver for Customer ASIC as Engineer @ (August 2003 - January 2006)
Development of UMTS transmitter as Graduate Research Assistant @ Advanced VLSI Design Laboratory (June 2002 - July 2003)
Prabal Mallick Education
Indian Institute of Technology, Kharagpur
Bachelor of Technology (Electronics and Electrical Communication)
1998-2002
Prabal Mallick Skills
RTL design
ASIC
Algorithms
FPGA
Verilog
Functional Verification
Testing
Mixed Signal
Debugging
Matlab
Integration
Prabal Mallick Summary
Prabal Mallick, based in Bhubaneswar, OD, IN, is currently a Principal Engineer at Signature IP ᵀᴹ. Prabal Mallick brings experience from previous roles at Lokawiz, Semtech, Ittiam Systems Pvt Ltd and Ittiam Systems (P) Ltd. Prabal Mallick holds a 1998 - 2002 Bachelor of Technology in Electronics and Electrical Communication @ Indian Institute of Technology, Kharagpur. With a robust skill set that includes RTL design, ASIC, Algorithms, FPGA, Verilog and more. Prabal Mallick has 1 emails and 1 mobile phone numbers on RocketReach.
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