Pooja Pathak Email
Member of Technical Staff @ AMD
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Pooja Pathak Location
- California, United States
Pooja Pathak Work
- 2022 -now Member of Technical Staff @
- 2021 -2022 ASIC Engineer @
- 2018 -2021 Sr. ASIC and Layout engineer @
- 2015 -2021 ASIC and Layout Design Engineer 2 @
- 2014 -2015 Verification Engineer (Contract) @
- 2013 -2014 Student Assistant at James Hunt Library @
- 2013 -2014 Graduate Student @
- 2012 -2012 Customer Service @ Scorpio Enterprise
- 2011 -2011 Design Engineer @ Bhuved Solutions Pvt. Ltd.
Pooja Pathak Education
- North Carolina State University
Master's degree (Computer Engineering)
2013-2014 - Vishwakarma Govt. Engineering college
B.E (Electronics and Communication)
2007-2011 - Mount Carmel High School 2000-2005
Pooja Pathak Skills
- C
- VHDL
- Embedded Systems
- Xilinx
- Matlab
- C++
- VLSI
- FPGA
- Verilog
- Assembly
- Labview
- PCB design
- Simulations
- Circuit Design
- Veri
- ASIC
- ASIC Verification
- Transaction level modelling
- SystemVerilog
- Microcontrollers
- Microprocessors
- Computer Architecture
- Manufacturing
- Transaction Level
- Computer Graphics
Pooja Pathak Summary
- Pooja Pathak, based in California, United States, is currently a Member of Technical Staff at AMD. Pooja Pathak brings experience from previous roles at Pensando Systems and AMD. Pooja Pathak holds a 2013 - 2014 Master's degree in Computer Engineering @ North Carolina State University. With a robust skill set that includes C, VHDL, Embedded Systems, Xilinx, Matlab and more. Pooja Pathak has 3 emails on RocketReach.
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