Pooja Patel Email
Circuit Design Engineer @ Vicharak
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Pooja Patel Location
- Surat, GJ, IN
Pooja Patel Work
- Circuit Design Engineer @ (August 2026 - Present)
- Circuit Design Engineer @ (June 2026 - August 2026)
- Circuit Design Intern @ (January 2026 - May 2026)
- Social Media Head @ (December 2024 - December 2025)
- Excutive Committee Member @ (January 2024 - December 2024)
- Summer Intern @ (May 2025 - July 2025)
Pooja Patel Education
- Nirma University
Bachelor of Technology - BTech (Electronics and Communications Engineering)
2022-2026 - Nirma University
Minor in Computer Science
Pooja Patel Skills
- Analog CMOS Design
- Cadence Genus
- Cadence Virtuoso
- Circuit Design
- Computer Architecture
- Custom Compiler
- Digital Image Processing
- Field-Programmable Gate Arrays (FPGA)
- MATLAB
- Machin Learning
- Python (Programming Language)
- Static Timing Analysis
- Verilog
- gem5
Pooja Patel Summary
- Pooja Patel, based in Surat, GJ, IN, is currently a Circuit Design Engineer at Vicharak. Pooja Patel brings experience from previous roles at Vicharak, Veevx, Inc. and ECO - Electronics and Communication Students' Organisation. Pooja Patel holds a 2022 - 2026 Bachelor of Technology - BTech in Electronics and Communications Engineering @ Nirma University. With a robust skill set that includes Analog CMOS Design, Cadence Genus, Cadence Virtuoso, Circuit Design, Computer Architecture and more.
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