Piyush Panwar Email & Phone Number
Principal Engineer - Design Verification @ Microchip Technology Inc.
Piyush Panwar's Location
Livermore, CA, US
Piyush Panwar's Work
- Principal Engineer - Design Verification @ Microchip Technology Inc.
- Sr. Verification Engineer @ Microchip Technology Inc.
- Hardware Engineer @ Cisco
- ASIC Design and Verification Engineer @ Arasan Chip Systems Inc.
- Technical Lab Assistant @ Santa Clara University
- Research Assistant @ Santa Clara University
- Grading Assistant @ Santa Clara University
- Intern @ Pragati Micro Instruments Pvt. Ltd
- Intern @ SATYAM
- Trainee @ Defence Electrcal Research Laboratory, DRDO
Piyush Panwar's Education
- Santa Clara University
Master's (Electrical Engineering)
2010 - 2012 - University of California, Santa Cruz
Certification (Electrical and Electronics Engineering)
2014 - 2015 - Jawaharlal Nehru Technological University
B.Tech (Electronics and Communication Engineering)
2005 - 2009
- Sheshagiri Rao Memorial junior college
MPC (Mathematics, Physics & Chemistry)
2002 - 2004 - Kendriya Vidyalaya
SSC (Physics, Mathematics)
1992 - 2002
Piyush Panwar's Skills
- Verilog
- VHDL
- Perl
- C
- ModelSim
- Logic Design
- SystemVerilog
- Integrated Circuit Design
- Static Timing Analysis
- RTL design
Piyush Panwar's Summary
Piyush Panwar, based in Livermore, CA, US, is currently a Principal Engineer - Design Verification at Microchip Technology Inc., bringing experience from previous roles at Microchip Technology Inc., Cisco Systems, Arasan Chip Systems Inc., and Santa Clara University. Piyush Panwar holds a 2010 - 2012 Master's in Electrical Engineering @ Santa Clara University. With a robust skill set that includes Verilog, VHDL, Perl, C, ModelSim and more, Piyush Panwar contributes valuable insights to the industry. Piyush Panwar has 2 emails and 1 mobile phone number on RocketReach.
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