Pierpaolo Valerio's Location
Geneva, GE, CH
Pierpaolo Valerio's Work
Pierpaolo Valerio's Education
Sapienza Università di Roma
Doctor of Philosophy (PhD) ( Electrical and Electronics Engineering)
2009 - 2013
Sapienza Università di Roma
Master of Engineering (M.Eng.) ( Electrical and Electronics Engineering, 110 (out of 110) cum laude and honorable mention from the committee.)
2007 - 2009
Sapienza Università di Roma
Bachelor of Engineering (B.Eng.) ( Electrical and Electronics Engineering, 110 (out of 110) cum laude.)
2003 - 2006
Pierpaolo Valerio's Skills
Pierpaolo Valerio's Summary
Pierpaolo Valerio, based in Geneva, GE, CH, is currently a Asic Designer at University of Geneva, bringing experience from previous roles at University of Geneva and Cern. Pierpaolo Valerio holds a 2009 - 2013 Doctor of Philosophy (PhD) in Electrical and Electronics Engineering @ Sapienza Università di Roma. With a robust skill set that includes Electronics, Linux, Cadence, Xilinx ISE, Matlab and more, Pierpaolo Valerio contributes valuable insights to the industry. Pierpaolo Valerio has 4 emails on RocketReach.