Phoebe Chen Email & Phone Number
Memory Interface Design @ Renesas Electronics
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Phoebe Chen Location
- California, United States
Phoebe Chen Work
- Memory Interface Design @ (January 2017 - Present)
- Micro-architect and SOC RTL low power design @ (June 2012 - January 2016)
- Hard IP RTL, Circuit design lead @ (January 2010 - January 2012)
- SOC Full Chip Timing Lead @ (January 2009 - January 2010)
- LCOS HDTV SRAM Design @ (January 2007 - January 2008)
Phoebe Chen Education
- The University of Texas at Austin
Bachelor's degree (Electrical and Electronics Engineering)
Phoebe Chen Skills
- Administrative Assistants
- Project Management
- System Administration
- Microsoft Office
- Microsoft Excel
- Outlook
- Process Improvement
- Windows
- Reliability
- Employee Relations
- VLSI
- EDA
- Embedded Systems
- Semiconductors
- Verilog
- ASIC
- SoC
- Debugging
- IC
- RTL design
- Low Power Design
- Static Timing Analysis
- FPGA
- Application Specific Integrated Circuits
- System on a Chip
- Very Large Scale Integration
- Field Programmable Gate Arrays
Phoebe Chen Summary
- Phoebe Chen, based in California, United States, is currently a Memory Interface Design at Renesas Electronics. Phoebe Chen brings experience from previous roles at Intel Corporation. Phoebe Chen holds a Bachelor's degree in Electrical and Electronics Engineering @ The University of Texas at Austin. With a robust skill set that includes Administrative Assistants, Project Management, System Administration, Microsoft Office, Microsoft Excel and more. Phoebe Chen has 2 emails and 1 mobile phone numbers on RocketReach.
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