2012 -
2016 Micro-architect and SOC RTL low power design @
2010 -
2012 Hard IP RTL, Circuit design lead @
2009 -
2010 SOC Full Chip Timing Lead @
2007 -
2008 LCOS HDTV SRAM Design @
Phoebe Chen Education
The University of Texas at Austin
Phoebe Chen Skills
Administrative Assistants
Project Management
System Administration
Microsoft Office
Microsoft Excel
Outlook
Process Improvement
Windows
Reliability
Employee Relations
VLSI
EDA
Embedded Systems
Semiconductors
Verilog
ASIC
SoC
Debugging
IC
RTL design
Low Power Design
Static Timing Analysis
FPGA
Application Specific Integrated Circuits
System on a Chip
Very Large Scale Integration
Field Programmable Gate Arrays
Phoebe Chen Summary
Phoebe Chen, based in California, United States, is currently a Memory Interface Design at Renesas Electronics. Phoebe Chen brings experience from previous roles at Intel Corporation. Phoebe Chen holds a The University of Texas at Austin. With a robust skill set that includes Administrative Assistants, Project Management, System Administration, Microsoft Office, Microsoft Excel and more. Phoebe Chen has 1 emails on RocketReach.
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