Phillip Ferguson Email & Phone Number
Chief FPGA Firmware Engineer @ Thales
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Phillip Ferguson Location
- Glasgow, GB
Phillip Ferguson Work
- Chief FPGA Firmware Engineer @ (September 2022 - Present)
- FPGA Engineer @ (November 2010 - September 2022)
- EngD Research Engineer @ (June 2006 - September 2010)
- Summer Academy Mentor @ (July 2005 - August 2005)
- Placement Student @ (June 2004 - September 2004)
Phillip Ferguson Education
- Institute for System Level Integration
Doctor of Engineering (System Level Integration)
2006-2010 - University of Strathclyde
MEng Electronic and Electrical Engineering with Business Studies (Distinction (1st Class))
2001-2006
Phillip Ferguson Skills
- Cadence Schematic Capture
- Altera Quartus
- Requirements Analysis
- Simul8
- Algorithms
- C
- Iec 61010
- Functional Verification
- Matlab
- Actel
- UVM
- Intel 8051
- IEC 61508
- OCP
- Agile Methodologies
- Xilinx ISE
- Zynq Ultrascale+ Mpsoc
- Verilog
- Scrum
- USB
- TCL
- CVS
- Edif
- Ethernet
- LaTeX
- Java
- Questasim
- VBA
- FPGA
- Assembler
- Reqtify
- Axi4
- Balsa
- VHDL
- ModelSim
- SystemVerilog
- Haste
- PCI Standards
- Do 254
- Research
- Hdl Designer
- Rmdb
- RTL verification
- CPLD
- Tortoise SVN
Phillip Ferguson Summary
- Phillip Ferguson, based in Glasgow, GB, is currently a Chief FPGA Firmware Engineer at Thales. Phillip Ferguson brings experience from previous roles at Thales Optronics Ltd, University of Strathclyde and National Semiconductor. Phillip Ferguson holds a 2006 - 2010 Doctor of Engineering in System Level Integration @ Institute for System Level Integration. With a robust skill set that includes Cadence Schematic Capture, Altera Quartus, Requirements Analysis, Simul8, Algorithms and more. Phillip Ferguson has 2 emails and 2 mobile phone numbers on RocketReach.
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