Philippe Maire Email
Senior prototyping Engineer @ ID4US
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Philippe Maire Location
- Grenoble, Auvergne-Rhône-Alpes, FR
Philippe Maire Work
- Senior prototyping Engineer @ (November 2023 - Present)
- Senior prototyping engineer @ (December 2021 - January 2024)
- Senior Prototyping Engineer @ (March 2020 - December 2021)
- Hardware and FPGA designer @ (August 2019 - March 2020)
- Design Engineer at IoT Sensors Excellence Center @ (May 2018 - August 2019)
- Senior Hardware Engineer @ (September 2015 - May 2018)
- Hardware and FPGA designer @ (May 2013 - September 2015)
- Hardware designer, project leader @ (March 2010 - September 2015)
- Synthesis STA Leader @ (February 2009 - February 2010)
- Synthesis and STA leader @ ST-NXP Wireless (January 2007 - February 2009)
- STA Leader @ (September 2007 - September 2008)
- Student engineer @ Adeunis RF (March 2007 - July 2007)
Philippe Maire Education
- Grenoble INP Esisar
Master of Engineering - MEng (Club Informatique ESISAR : President for 2 years)
2002-2007 - University of Southampton
(Electronics and Computer Science)
2006-2007
Philippe Maire Skills
- Static Timing Analysis
- VHDL
- PCB design
- Electronics
- FPGA
- Embedded Systems
- Xilinx
- Altera
- Hardware
- RF
- Infrared Thermal Imaging
- Image Acquisition
- Video Processing
- DDR3
- Power Supplies
- MSP430
- Microcontrollers
- HDMI
- Camera Link
- Marc
- Electronic Hardware
Philippe Maire Summary
- Philippe Maire, based in Grenoble, Auvergne-Rhône-Alpes, FR, is currently a Senior prototyping Engineer at ID4US. Philippe Maire brings experience from previous roles at Huawei, ISORG and Schneider Electric. Philippe Maire holds a 2002 - 2007 Master of Engineering - MEng in Club Informatique ESISAR : President for 2 years @ Grenoble INP Esisar. With a robust skill set that includes Static Timing Analysis, VHDL, PCB design, Electronics, FPGA and more. Philippe Maire has 2 emails on RocketReach.
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