Philippe Maire Email
Senior prototyping Engineer @ ID4US
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Philippe Maire Location
- Grenoble, Auvergne-Rhône-Alpes, FR
Philippe Maire Work
- 2023 -now Senior prototyping Engineer @
- 2021 -2024 Senior prototyping engineer @
- 2020 -2021 Senior Prototyping Engineer @
- 2019 -2020 Hardware and FPGA designer @
- 2018 -2019 Design Engineer at IoT Sensors Excellence Center @
- 2015 -2018 Senior Hardware Engineer @
- 2013 -2015 Hardware and FPGA designer @
- 2010 -2015 Hardware designer, project leader @
- 2009 -2010 Synthesis STA Leader @
- 2007 -2009 Synthesis and STA leader @ ST-NXP Wireless
- 2007 -2008 STA Leader @
- 2007 -2007 Student engineer @ Adeunis RF
Philippe Maire Education
- Grenoble INP Esisar
Master of Engineering - MEng (Club Informatique ESISAR : President for 2 years)
2002-2007 - University of Southampton
(Electronics and Computer Science)
2006-2007
Philippe Maire Skills
- Static Timing Analysis
- VHDL
- PCB design
- Electronics
- FPGA
- Embedded Systems
- Xilinx
- Altera
- Hardware
- RF
- Infrared Thermal Imaging
- Image Acquisition
- Video Processing
- DDR3
- Power Supplies
- MSP430
- Microcontrollers
- HDMI
- Camera Link
- Marc
- Electronic Hardware
Philippe Maire Summary
- Philippe Maire, based in Grenoble, Auvergne-Rhône-Alpes, FR, is currently a Senior prototyping Engineer at ID4US. Philippe Maire brings experience from previous roles at Huawei, ISORG and Schneider Electric. Philippe Maire holds a 2002 - 2007 Master of Engineering - MEng in Club Informatique ESISAR : President for 2 years @ Grenoble INP Esisar. With a robust skill set that includes Static Timing Analysis, VHDL, PCB design, Electronics, FPGA and more. Philippe Maire has 2 emails on RocketReach.
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