Philip Pun Email & Phone Number
Sr. Engineer @ General Atomics
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Philip Pun Location
- San Jose, CA, US
Philip Pun Work
- 2024 -now Sr. Engineer @
- 2023 -2024 PCB Design Lead @
- 2019 -2023 Staff Electrical Engineer @
- 2015 -2019 Sr. H and W Design Engineer @
- 2014 -2015 Principal Design Engineer - LPDDR and DDR Interfaces, Test Boards, SI and PI, Chip and Package Co-Design @
- 2006 -2013 Technical Leader - SoC+Package+PCB Co-Design - Signal and Power Integrity @
- 1988 -2006 Sr. Staff Circuit Design Engineer @ Integrated Circuit & ASIC Design
Philip Pun Education
- Univ of Southern California
Master of Science (M.S.) (Electrical Engineering)
Philip Pun Skills
- I/O Library Development
- Hardware
- Routing
- Io Layout
- Program Management
- Strategic Planning
- Leadership
- Package Design
- Testing
- Analog Layout
- SoC
- CMOS
- Engineering
- Packaging
- Graphic Design
- Logic Cell Library Development
- Business Development
- Customer Service
- ASIC
- PCB design
- Systems Design
- Hardware Engineering
- Management
- VLSI
- IC
- Signal Integrity
- Integrity
- Physical Design
- Hardware Architecture
- Circuit Design
- EDA
- Design
- SPICE
- High Speed Io Interfaces
- SERDES
- Io and Esd Design
- Power Integrity
- Co Design
- Application Specific Integrated Circuits Asic
Philip Pun Summary
- Philip Pun, based in San Jose, CA, US, is currently a Sr. Engineer at General Atomics. Philip Pun brings experience from previous roles at General Radar Corp., Joby Aviation, Apple and Cadence Design Systems. Philip Pun holds a Master of Science (M.S.) in Electrical Engineering @ Univ of Southern California. With a robust skill set that includes I/O Library Development, Hardware, Routing, Io Layout, Program Management and more. Philip Pun has 2 emails and 1 mobile phone numbers on RocketReach.
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