Mixed Signal IC Designer and Layout Engineer @ Cactus Semiconductor (July 2012 - Present)
IC Mixed Signal Design Engineer @ (March 2009 - May 2012)
Engineering Director, Design Manager @ (April 1999 - March 2009)
Design Manager, IC Design Engineer @ Motorola Inc (January 1979 - April 1999)
Phil Jeffery Education
Arizona State University
Master of Science (MS) (Electrical and Electronics Engineering)
1986-1990
University of California, Berkeley
Bachelor of Science (BS) (Electrical Engineering and Computer Science)
1976-1978
Phil Jeffery Skills
DRC
Design
30+ Years Experience In The Design Of High Performance Products
Mixed Signal
Positive Attitude
CMOS
LVS
BiCMOS
Layout
Experienced In Ic Layout
Proficient With Cadence And Mentor Design Tools
PLL
Results Oriented
Proficient With Lab Equipment To Characterize Device Performance
Cadence
Drc And Mask Submission
IC layout
Mixed Signal Design
Excellent Office And Communication Skills
IC
Phil Jeffery Summary
Phil Jeffery, based in Tempe, AZ, US, is currently a Staff Layout Engineer at asicNorth. Phil Jeffery brings experience from previous roles at Cactus Semiconductor, ON Semiconductor and Motorola Inc. Phil Jeffery holds a 1986 - 1990 Master of Science (MS) in Electrical and Electronics Engineering @ Arizona State University. With a robust skill set that includes DRC, Design, 30+ Years Experience In The Design Of High Performance Products, Mixed Signal, Positive Attitude and more. Phil Jeffery has 1 mobile phone numbers on RocketReach.
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