Phani S Email
Design Verification Engineer @ Analog Devices
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Phani S Location
- Hyderabad, IN
Phani S Work
- 2024 -now Design Verification Engineer @
- 2024 -2024 DV Intern @
- 2013 -2015 Analyst @ Deloitte Services LLP
Phani S Education
- National Institute of Technology Karnataka
Master of Technology - MTech (Communication Engineering and Networks)
2022-2024 - Osmania University, Hyderabad
Bachelor of Engineering - BE (Electronics and Communications Engineering)
2009-2013
Phani S Skills
- Functional Verification
- Formal Verification
- Universal Verification Methodology (UVM)
- System Verilog
- Xilinx Vivado
- MATLAB
- C (Programming Language)
- Verilog
- Advanced Business Application Programming (ABAP)
- Object Oriented ABAP (OOABAP)
Phani S Summary
- Phani S, based in Hyderabad, IN, is currently a Design Verification Engineer at Analog Devices. Phani S brings experience from previous roles at Analog Devices India and Deloitte Services LLP. Phani S holds a 2022 - 2024 Master of Technology - MTech in Communication Engineering and Networks @ National Institute of Technology Karnataka. With a robust skill set that includes Functional Verification, Formal Verification, Universal Verification Methodology (UVM), System Verilog, Xilinx Vivado and more. Phani S has 2 emails on RocketReach.
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