Peter Nagey Email & Phone Number
Analog Senior Design Engineering Manager @ Microchip Technology Inc.
Peter Nagey's Location
Tempe, Arizona, United States
Peter Nagey's Work
- Analog Senior Design Engineering Manager @ Microchip Technology Inc.
- Analog Engineering Design Manager @ Microchip Technology Inc.
- Analog Design Engineer @ Confidential Startup in Stealth Mode
- Senior Staff Analog Design Engineer @ SiRF Technology
- Senior Staff Design Engineer @ NXP acquires Freescale Semiconductor
- Senior Member of Technical Staff @ Maxim Integrated
- Mram Design Manager @ Motor X
- Product Development Engineer @ National Semiconductor
- Staff Design Engineer @ NXP acquires Freescale Semiconductor
- Design Engineer @ onsemi
Peter Nagey's Education
- University of Idaho
Master of Science in Electrical Engineering (Electrical Engineering)
1996 - University of Utah
Bachelor of Science (Electrical Engineering, Applied Physics)
1985 - 1989
Peter Nagey's Summary
Peter Nagey, based in Tempe, Arizona, United States, is currently a Analog Senior Design Engineering Manager at Microchip Technology, bringing experience from previous roles at Microchip Technology, Confidential Startup in Stealth Mode, Sirf Technology and Freescale Semiconductor. Peter Nagey holds a Master of Science in Electrical Engineering in Electrical Engineering @ University of Idaho. Peter Nagey has 1 email on RocketReach.
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