Peter Kovacs Location
- Santa Clara, CA, US
Peter Kovacs Work
- 2023 -now Senior Design Engineer @
- 2022 -2023 Principal Design Engineer @
- 2015 -2022 Senior Wireless RTL Design Engineer @
- 2008 -2015 Wireless DSP engineer @
- 2007 -2008 DSP Engineer @ evoSoft
- 2005 -2007 Wireless DSP-engineer @
Peter Kovacs Education
- Budapesti Mûszaki és Gazdaságtudományi Egyetem 2000-2005
Peter Kovacs Skills
- SoC
- FPGA
- ASIC
- Verilog
- ModelSim
- Functional Verification
- Integrated Circuit Design
- RTL design
- SystemVerilog
- RTL coding
- Microcontrollers
- Digital Signal Processors
- Embedded Systems
- Simulations
- Logic Synthesis
- Application-Specific Integrated Circuits (ASIC)
- Signal Processing
- Field-Programmable Gate Arrays (FPGA)
- Digital Signal Processing
- Wireless Technologies
- C
- DFT
- Field Programmable Gate Arrays Fpga
- Data Validation
- Application Specific Integrated Circuits Asic
- DSP
- Semiconductors
- Design
- Wireless
- Architecture
- Application Specific Integrated Circuits
- Field Programmable Gate Arrays
Peter Kovacs Summary
- Peter Kovacs, based in Santa Clara, CA, US, is currently a Senior Design Engineer at Apple. Peter Kovacs brings experience from previous roles at Analog Devices, Intel Corporation, Microchip Technology and evoSoft. Peter Kovacs holds a 2000 - 2005 Budapesti Mûszaki és Gazdaságtudományi Egyetem. With a robust skill set that includes SoC, FPGA, ASIC, Verilog, ModelSim and more. Peter Kovacs has 2 emails and 1 mobile phone numbers on RocketReach.
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