Peter Jancso's Location
Budapest, Budapest, Hungary
Peter Jancso's Work
- Fpga Design Engineer @ Benetel
- Senior Development Consultant @ Qamcom Research & Technology Central Europe
- Project Engineer and Fpga Team Leader @ NORBIT ASA
- Fpga Design Engineer @ Ericsson
- Hardware Development Engineer @ Mentor Graphics
- Trainee Ic Design @ Silicon Labs
Peter Jancso's Education
- Budapest University of Technology and Economics
Master of Science
2003 - 2008
Peter Jancso's Skills
- Systems Design
- Mad
- C
- RTL design
- PCB design
- Electronics
- System Design
- Verilog
- ClearCase
- Xilinx
Peter Jancso's Summary
Peter Jancso, based in Budapest, Budapest, Hungary, is currently a Fpga Design Engineer at Benetel, bringing experience from previous roles at Qamcom Research & Technology Central Europe, Norbit Group, Ericsson and Mentor Graphics. Peter Jancso holds a 2003 - 2008 Master of Science @ Budapest University of Technology and Economics. With a robust skill set that includes Systems Design, Mad, C, RTL design, PCB design and more, Peter Jancso contributes valuable insights to the industry. Peter Jancso has 3 emails on RocketReach.
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