Peter Hsueh Email & Phone Number
Director, Systems Validation @ Marvell India
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Peter Hsueh Location
- California, United States
Peter Hsueh Work
- Director, Systems Validation @ (September 2019 - Present)
- Director, QA @ Aquantia (June 2017 - September 2019)
- Manager, Hardware Engineering @ (September 2016 - June 2017)
- Consult Hardware Engineer, Test and Validation @ (October 2014 - September 2016)
- Senior Engineering Manager, Systems and Validation @ Aquantia (July 2012 - September 2014)
- Senior Member of Technical Staff @ Aquantia (March 2008 - June 2012)
- Ethernet Validation Technical Lead @ (April 2007 - March 2008)
- Senior Hw Validation Engineer, Physical Layer Ics @ (January 2004 - April 2007)
- Applications Engineer, Physical Layer Ics @ (April 2001 - January 2004)
- Customer Design Engineering Intern @ (January 2000 - September 2000)
Peter Hsueh Education
- University of California - Davis
Bachelor Of Science (Electrical Engineering)
Peter Hsueh Skills
- Test Management
- IC
- Demos
- Debugging
- Analog
- Testing
- SERDES
- Mixed Signal
- PCB design
- Oscilloscope
- SoC
- ASIC
- Ethernet
- CMOS
- Embedded Systems
- FPGA
- Semiconductors
- Verilog
- Hardware
- Integrated Circuits (IC)
Peter Hsueh Summary
- Peter Hsueh, based in California, United States, is currently a Director, Systems Validation at Marvell Semiconductor. Peter Hsueh brings experience from previous roles at Aquantia and Dell Emc. Peter Hsueh holds a Bachelor Of Science in Electrical Engineering @ University of California - Davis. With a robust skill set that includes Test Management, IC, Demos, Debugging, Analog and more. Peter Hsueh has 2 emails and 1 mobile phone numbers on RocketReach.
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