Peter Hsu Email & Phone Number

Peter Hsu Skills

• IC
• Semiconductors
• SoC
• ASIC
• Semiconductor Industry
• Mixed Signal
• Integrated Circuit Design
• L3 SRAM Cache, SRAM compiler, 1T SRAM, embedded DRAM, DRAM, DLL/PLL clock Gen.
• A SRAM Cell Array Adaptive leakage reduction ...Paper 2012 VLSI Symposium
• High bandwidth random access specialty DRAM design
• 92 US patents issued
• System on a Chip (SoC)
• Debugging
• Verilog
• Silicon
• CMOS
• VLSI
• FPGA
• 1t Sram
• SRAM
• System on a Chip Soc
• L3 Sram Cache
• 83 Us Patents Issued
• Integrated Circuit
• A Sram Cell Array
• Sram Compiler
• Dll/Pll Clock Gen
• 76 Us Patents Issued
• 66 Us Patent Issued
• DRAM
• Embedded Dram
• System on a Chip