Pete Ippolito Email & Phone Number
SMTS and uArch and SOC Power Analysis and Optimization @ NXP Semiconductors
Pete Ippolito's Location
Austin, TX, US
Pete Ippolito's Work
- SMTS and uArch and SOC Power Analysis and Optimization @ NXP Semiconductors
- MTS and CPU Power Analysis and Optimization @ Oracle
- SMTS and SPARC CPU Integration Manager @ Oracle
- SMTS and Integration Manager @ Intel Corporation
- MTS and CPU Integration @ NXP acquires Freescale Semiconductor
- MTS and Full Chip Integration @ ESS Technology, Inc.
- I-cache Implementation Lead and SRAM Designer @ Equator Technologies
- Staff Engineer and Circuit Designer @ IBM - Somerset Design Center
Pete Ippolito's Education
- UCLA
MSEE (Electrical Engineering)
- Princeton University
BSEE (Electrical Engineering)
Pete Ippolito's Skills
- Logic Design
- Cadence Virtuoso
- Computer Architecture
- Floorplanning
- SRAM
- Algorithms
- Debugging
- SPICE
- Functional Verification
- Perl
Pete Ippolito's Summary
Pete Ippolito, based in Austin, TX, US, is currently a SMTS and uArch and SOC Power Analysis and Optimization at NXP Semiconductors, bringing experience from previous roles at Oracle Microelectronics, Intel Corporation and Freescale Semiconductor Corporation. Pete Ippolito holds a MSEE in Electrical Engineering @ UCLA. With a robust skill set that includes Logic Design, Cadence Virtuoso, Computer Architecture, Floorplanning, SRAM and more, Pete Ippolito contributes valuable insights to the industry. Pete Ippolito has 2 emails on RocketReach.
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