Pervez Garg's Location
Bengaluru, KA, IN
Pervez Garg's Work
- DFT Manager @ Texas Instruments
- Sr Digital Design Engineer @ Texas Instruments
- Design Engineer @ Texas Instruments
- Intern @ Texas Instruments
- Intern @ Central Scientific Instruments Organization
Pervez Garg's Education
- Birla Institute of Technology and Science
B.E.(Hons.) (EEE)
2006 - 2010
Pervez Garg's Skills
- VLSI
- RTL design
- ASIC
- SoC
- Static Timing Analysis
- Matlab
- ModelSim
- Design
- Digital Design
- Consumer Electronics
Pervez Garg's Summary
Pervez Garg, based in Bengaluru, KA, IN, is currently a DFT Manager at Texas Instruments, bringing experience from previous roles at Texas Instruments and Central Scientific Instruments Organization. Pervez Garg holds a 2006 - 2010 B.E.(Hons.) in EEE @ Birla Institute of Technology and Science. With a robust skill set that includes VLSI, RTL design, ASIC, SoC, Static Timing Analysis and more, Pervez Garg contributes valuable insights to the industry. Pervez Garg has 2 emails and 2 mobile phone numbers on RocketReach.
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