Peer Schmitt Location
France
Peer Schmitt Work
- 2011 - now FPGA technologist @ ADICSYS
- 2006 - 2010 FPGA architect and team lead @ Abound Logic
- 2001 - 2006 ASIC design and FPGA architect @ Mentor Graphics
- 1999 - 2001 ASIC design engineer @ Intel Corporation
- 1999 - 1999 ASIC design engineer @ Bull
Peer Schmitt Education
- ISEP - école d'ingénieurs du numérique
Master of Science in Electrical Engineering
1994 - 1997 (Mathematics)
1992 - 1994
Peer Schmitt Skills
- CAD
- RTL design
- Physical Design
- SoC
- FPGA
- Digital Design
- ASIC
- Verilog
- Static Timing Analysis
- EDA
Peer Schmitt Summary
Peer Schmitt, based in France, is currently a FPGA technologist at ADICSYS. Peer Schmitt brings experience from previous roles at Abound Logic, Mentor graphics, Intel Corp. and BULL. Peer Schmitt holds a 1994 - 1997 Master of Science in Electrical Engineering @ ISEP - école d'ingénieurs du numérique. With a robust skill set that includes CAD, RTL design, Physical Design, SoC, FPGA and more. Peer Schmitt has 1 emails on RocketReach.
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