Peer Schmitt Email
FPGA technologist @ ADICSYS
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Peer Schmitt Location
- France
Peer Schmitt Work
- FPGA technologist @ (February 2011 - Present)
- FPGA architect and team lead @ Abound Logic (October 2006 - May 2010)
- ASIC design and FPGA architect @ (July 2001 - September 2006)
- ASIC design engineer @ (December 1999 - June 2001)
- ASIC design engineer @ (January 1999 - December 1999)
Peer Schmitt Education
- ISEP - école d'ingénieurs du numérique
Master of Science in Electrical Engineering
1994-1997 -
(Mathematics)
1992-1994
Peer Schmitt Skills
- CAD
- RTL design
- Physical Design
- SoC
- FPGA
- Digital Design
- ASIC
- Verilog
- Static Timing Analysis
- EDA
- Timing Closure
- IC
- LVS
- Physical Verification
- Circuit Design
- TCL
- VHDL
- Low Power Design
- DFT
- ModelSim
- RTL coding
- Functional Verification
- Floorplanning
- Logic Design
- VLSI
- Debugging
- Semiconductors
- Primetime
- Simulation
- CMOS
- Timing
- ATPG
- Perl
- Signal Integrity
- DRC
- Integrated Circuit Design
- Emulation
- SystemVerilog
- Cadence
- Logic Synthesis
- System Architecture
- Sales
- Microsoft Office
- SQL
Peer Schmitt Summary
- Peer Schmitt, based in France, is currently a FPGA technologist at ADICSYS. Peer Schmitt brings experience from previous roles at Abound Logic, Mentor graphics, Intel Corp. and BULL. Peer Schmitt holds a 1994 - 1997 Master of Science in Electrical Engineering @ ISEP - école d'ingénieurs du numérique. With a robust skill set that includes CAD, RTL design, Physical Design, SoC, FPGA and more. Peer Schmitt has 2 emails on RocketReach.
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