Pawan Pareek Email

Pawan Pareek Email

Asic Design Verification Engineer @ Google

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Pawan Pareek's Location

Bengaluru, KA, IN

Pawan Pareek's Work

Pawan Pareek's Education

  • IIT Bombay

    Master of Technology (M.Tech.) ( Microelectronics and VLSI Design, CGPA (9.44/10))

    2012 - 2014
  • The LNMIIT

    Bachelor of Technology (B.Tech.) ( Electrical, Electronics and Communications Engineering)

    2007 - 2011

Pawan Pareek's Skills

  • Matlab
  • Verilog
  • C
  • VHDL
  • Algorithms
  • ModelSim
  • Linux
  • SystemVerilog
  • Analog Circuit Design
  • FPGA

Pawan Pareek's Summary

Pawan Pareek, based in Bengaluru, KA, IN, is currently a Asic Design Verification Engineer at Google, bringing experience from previous roles at Qualcomm, Samsung and Cisco. Pawan Pareek holds a 2012 - 2014 Master of Technology (M.Tech.) in Microelectronics and VLSI Design, CGPA (9.44/10) @ IIT Bombay. With a robust skill set that includes Matlab, Verilog, C, VHDL, Algorithms and more, Pawan Pareek contributes valuable insights to the industry. Pawan Pareek has 2 emails on RocketReach.
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