Pavan S Email
Design Verification Engineer @ Synopsys Inc
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Pavan S Location
- United States
Pavan S Work
- 2019 -now Design Verification Engineer @
- 2017 -2018 IP Verification @
- 2016 -2017 SOC Design Verification @
- 2010 -2016 Verification and Methodology engineer @
Pavan S Skills
- RTL Verification
- SystemVerilog
- ModelSim
- Perl
- Verilog
- ASIC
- Functional Verification
- RTL design
- Debugging
- NCSim
- VLSI
- USB
- Physical Verification
- LVS
- DRC
- Simulations
- SoC
- EDA
- VHDL
- Testing
- VCS
- UVM
- System on a Chip (SoC)
- Application-Specific Integrated Circuits (ASIC)
- Universal Verification Methodology (UVM)
- Very-Large-Scale Integration (VLSI)
- Formal Verification
Pavan S Summary
- Pavan S, based in United States, is currently a Design Verification Engineer at Synopsys Inc. Pavan S brings experience from previous roles at Qualcomm and NXP Semiconductors. With a robust skill set that includes RTL Verification, SystemVerilog, ModelSim, Perl, Verilog and more. Pavan S has 2 emails on RocketReach.
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