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Pavan Rayapati Location
San Jose, CA, US
Pavan Rayapati Work
2024 -now Senior DFT Engineer - L2 @
2023 -2024 Senior DFT Engineer - L1 @
2022 -2023 Senior DFT Engineer @
2019 -2022 Product Development Engineer - 1 @
2018 -2019 VLSI TRAINING @
2018 -2019 Internship Trainee @
Pavan Rayapati Education
Devineni Venkata Ramana & Dr. Hima Sekhar MIC College of Technology, Kanchikacherla, PIN-521180(CC-H7)
Bachelor of Technology (Electrical and Electronics Engineering)
2014-2018
Pavan Rayapati Skills
ATE Pattern delivery
Tessent mbist
EBIST
Compression
Scan
mbist
Design Rule Checking (DRC)
Coverages
DFT
Very-Large-Scale Integration (VLSI)
Electronics
Semiconductors
Strategic Planning
Creative Writing
Engineering
Field-Programmable Gate Arrays (FPGA)
Application-Specific Integrated Circuits (ASIC)
System on a Chip (SoC)
Simulations
Microsoft Office
Matlab
Linux
Verilog
Communication
Teamwork
English
SV
Universal Verification Methodology (UVM)
Static Timing Analysis
RTL Coding
RTL Design
system verilog
basic perl
Logic Synthesis
RTL Verification
Assertion Based Verification
Functional Verification
DDR4SDRAM
Relays
Automatic Test Pattern Generation (ATPG)
sdf
Pavan Rayapati Summary
Pavan Rayapati, based in San Jose, CA, US, is currently a Senior DFT Engineer - L2 at Anora. Pavan Rayapati brings experience from previous roles at Anora and Maven Silicon. Pavan Rayapati holds a 2014 - 2018 Bachelor of Technology in Electrical and Electronics Engineering @ Devineni Venkata Ramana & Dr. Hima Sekhar MIC College of Technology, Kanchikacherla, PIN-521180(CC-H7). With a robust skill set that includes ATE Pattern delivery, Tessent mbist, EBIST, Compression, Scan and more. Pavan Rayapati has 2 emails on RocketReach.
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