Pavan Badiger Email & Phone Number

Pavan Badiger Skills

• Verilog
• VLSI
• DFT
• TCL
• SystemVerilog
• Perl
• VHDL
• ATPG
• Logic Synthesis
• Mixed Signal
• ASIC
• Cadence
• DRC
• Scan Insertion
• Low-power Design
• Analog
• BIST
• ModelSim
• RTL Design
• Cadence Spectre
• Debugging
• Integrated Circuit Design
• Synthesis
• Memory Test
• Aldec
• Application-Specific Integrated Circuits (ASIC)
• C
• Very-Large-Scale Integration (VLSI)
• Automatic Test Pattern Generation (ATPG)
• Information Technology
• Solutions
• Integrated Circuit
• Application Specific Integrated Circuits Asic
• Automatic Test Pattern Generation Atpg
• Low Power Design
• Very Large Scale Integration Vlsi
• Code Coverage
• Very Large Scale Integration
• Application Specific Integrated Circuits
• Automatic Test Pattern Generation