Paul Vella Email & Phone Number
PMTS ASIC and Layout Design Engineer @ AMD
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Paul Vella Location
- Boxborough, MA, US
Paul Vella Work
- 2023 -now PMTS ASIC and Layout Design Engineer @
- 2006 -2023 SMTS ASIC and Layout Design Engineer @
- 1998 -2006 Senior Hardware Designer @
Paul Vella Education
- Worcester Polytechnic Institute
masters (Computer Engineering)
2000-2005 - Worcester Polytechnic Institute
bachelors (Computer Engineering)
1994-1998
Paul Vella Skills
- RTL design
- ASIC
- Static Timing Analysis
- Timing Closure
- Debugging
- Verilog
- Computer Architecture
- SystemVerilog
- Microprocessors
- Functional Verification
- Hardware Architecture
- SoC
- Processors
- Primetime
- VLSI
- Physical Design
- Semiconductors
- Formal Verification
- RTL coding
- EDA
- VHDL
- DFT
- TCL
- Perl
- Layout Design
- Design
- Verification
Paul Vella Summary
- Paul Vella, based in Boxborough, MA, US, is currently a PMTS ASIC and Layout Design Engineer at AMD. Paul Vella brings experience from previous roles at AMD. Paul Vella holds a 2000 - 2005 masters in Computer Engineering @ Worcester Polytechnic Institute. With a robust skill set that includes RTL design, ASIC, Static Timing Analysis, Timing Closure, Debugging and more. Paul Vella has 3 emails and 1 mobile phone numbers on RocketReach.
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